[Synopsys - HCM] Physical Design Engineer

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☞ Synopsys Vietnam

見る: 199

更新日: 14-04-2024

場所: Ho Chi Minh

カテゴリー: 機械/技術 電気/電子工学 IT-ハードウェア/ネットワーキング

レベル: Nhân viên

給料: 1,000 - 4,000 USD

教育: Đại học

経験: 1 - 10 Năm

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仕事内容

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

We’re looking for a Physical Design Engineer to join the team.
In this role, you will be responsible for the Physical implementation of high speed interface IPs, sub-system, and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off, in close interaction and collaborative team work with multiple functional groups (front end, analog, CAD) and the product team .

Responsibilities:

  • The role involves daily technical interaction with local, US counter parts.
  • Will be part of SNPS DDR, HBI IP implementation team and responsible for the implementation and integration of world class Die-to-Die IPs at the cutting-edge technology nodes (14nm,10nm,7nm and below).
  • Timing closure above ~2GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job.
  • Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage.

仕事の要件

  • From 1yearof physical design experience with recent contribution to project tape-outs.
  • Should be strong in technical concepts, fundamentals, and good team player.
  • This role is for a technical ladder and so it requires hands-on working knowledge preferably with SNPS tools like DC, PT, PT-SI and ICC2
  • Has intimate knowledge of the full design cycle from RTL to GDSII, including chip level.
  • Has solid engineering understanding of the underlying concepts of IC design, implementation flows and methodologies for deep submicron design.
  • Has good communication skills, ability to think and communicate at different levels of abstraction with peer groups.
  • Must demonstrate knowledge of the Synopsys tools, flows and methodologies required to execute physical design projects. These tools may include: Design Compiler, Physical Compiler, Primetime SI, ICC/ICC2, Star-RCXT, ICV, and other tools.
  • Has good software and scripting skills (Perl, Tcl, Python); knowledge of CAD automation methods.
  • Autonomous, timely decision maker and able to cope with interrupts

仕事上の利点

  • Laptop
  • Chế độ bảo hiểm
  • Du Lịch
  • Phụ cấp
  • Du lịch nước ngoài
  • Chế độ thưởng
  • Chăm sóc sức khỏe
  • Đào tạo
  • Tăng lương
  • Nghỉ phép năm
  • CLB thể thao
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締切: 14-05-2024

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