Synopsys HCMC - Design Verification Engineer (Mid-Senior)

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☞ Synopsys Vietnam

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更新日: 04-05-2024

場所: Ho Chi Minh

カテゴリー: 電気/電子工学 IT-ハードウェア/ネットワーキング

レベル: Nhân viên

給料: Cạnh tranh

教育: Đại học

経験: 2 - 5 Năm

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仕事内容

Business Area Description

The Solutions Group high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

Opportunities

  • SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team
  • Professional, innovative, fair and fun working environment. Strong culture company.
  • Competitive salary and benefit. Dedicated support from company for health: Insurance, Sport clubs: Football, Table-tennis, Badminton, Yoga, Zumba …
  • Dedicated support from company for team building, social activities: Team trip, Family Day…
  • Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
  • Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications.
  • Clear career path of self-development to either Technical Expert or Design Leader/Manager

Job Descriptions

  • Develop and review verification plan
  • Create testcase and perform RTL verification using SystemVerilog, UVM
  • Debug the failing testcase, work with RTL design team analyze the root-cause
  • Perform and evaluate verification regression
  • Perform gate-level simulation with SDF back-annotation

仕事の要件

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 2+ years of experience in Design Verification
  • Familiar with design verification flow at IP or SoC level
  • Knowledge of SystemVerilog, UVM, and complex module testbench is a big plus
  • Knowledge of Analog Mixed Signal design, High-Speed Interface IP is a big plus
  • Good debugging capability and problem-solving skills

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

仕事上の利点

  • Laptop
  • Chế độ bảo hiểm
  • Du Lịch
  • Phụ cấp
  • Chế độ thưởng
  • Chăm sóc sức khỏe
  • Đào tạo
  • Tăng lương
  • Nghỉ phép năm
  • CLB thể thao
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締切: 03-06-2024

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