Synopsys HCMC - Design Verification Engineer (Mid-Senior)

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☞ Synopsys Vietnam

视图: 145

更新日: 14-04-2024

位置: Ho Chi Minh

类别: 电气/电子 IT-硬件/网络

水平: Nhân viên

薪水: Cạnh tranh

水平: Đại học

经验: 2 - 5 Năm

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职位描述

Business Area Description

The Solutions Group high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

Opportunities

  • SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team
  • Professional, innovative, fair and fun working environment. Strong culture company.
  • Competitive salary and benefit. Dedicated support from company for health: Insurance, Sport clubs: Football, Table-tennis, Badminton, Yoga, Zumba …
  • Dedicated support from company for team building, social activities: Team trip, Family Day…
  • Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
  • Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications.
  • Clear career path of self-development to either Technical Expert or Design Leader/Manager

Job Descriptions

  • Develop and review verification plan
  • Create testcase and perform RTL verification using SystemVerilog, UVM
  • Debug the failing testcase, work with RTL design team analyze the root-cause
  • Perform and evaluate verification regression
  • Perform gate-level simulation with SDF back-annotation

工作要求

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 2+ years of experience in Design Verification
  • Familiar with design verification flow at IP or SoC level
  • Knowledge of SystemVerilog, UVM, and complex module testbench is a big plus
  • Knowledge of Analog Mixed Signal design, High-Speed Interface IP is a big plus
  • Good debugging capability and problem-solving skills

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

工作兴趣

  • Laptop
  • Chế độ bảo hiểm
  • Du Lịch
  • Phụ cấp
  • Chế độ thưởng
  • Chăm sóc sức khỏe
  • Đào tạo
  • Tăng lương
  • Nghỉ phép năm
  • CLB thể thao
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最后期限: 14-05-2024

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